The present invention relates to a method and/or architecture for implementing output buffer control generally and, more particularly, to a method and/or architecture for implementing a dual tristate path output buffer control.
Synchronous random access memories (RAMs) use clock signals to control (enable/disable) output buffers. Conventional synchronous RAMs have maximum time delay specifications for the propagation of the clock signal to the output buffer when the output buffer control circuit (i.e., a tristate register) is in a low impedance state (i.e., Tclz) and when the output buffer control circuit is in a high impedance state (i.e., Tchz). The Tclz and Tchz parameters often have the same time delay specification as a clock control circuit to valid output timing specification when the RAM is in a pipelined mode (i.e., Tco).
Referring to FIG. 1, a block diagram illustrating a conventional clock signal to output buffer control circuit 10 is shown. The circuit 10 is coupled to a RAM 12. The circuit 10 can be common to all RAM outputs. The circuit 10 has an input 14 that receives a clock signal (i.e., CLK), an input 16 that receives a first control signal (i.e., CNTL), an input 17 that receives a second control signal (i.e., CNTL2), and an output 18 that presents a signal (i.e., IO). The signal ENABLE is the RAM 12 output enable/disable signal. The signal CNTL controls the signal ENABLE in response to (i.e., as a function of) signals such as chip enable, write enable, etc. The signal IO is the memory output signal. The signal ENABLE only changes on the rising edge of the signal CLK if the signal CTRL has changed since the previous rising edge of the signal CLK.
The circuit 10 includes a controller 20, a Tclz/Tchz path circuit 22, a Tco path circuit 24, and an output buffer 26. The controller 20 is often implemented at the physical center of the RAM 12. The controller 20 is coupled to the output buffer 26 via the paths 22 and 24. The controller 20 is typically implemented as a tristate register 30 and a Tco gate 32. The Tco gate 32 is typically implemented as an AND gate. The register 30 controls the enabled/disabled state of the output buffer 26 in response to the signals CLK and CNTL. The paths 22 and 24 include a number of amplifiers/buffers (or inverting amplifiers/buffers) and RC elements (i.e., metal interconnect parasitic delays). The output buffer 26 includes a buffer circuit 40 and a Tco register 42. The buffer 40 has a data input that receives the signal IO, an enable input that receives the signal ENABLE, and an output that presents the signal IO.
The register 30 has inputs that receive the signals CLK and CNTL and an output that presents the signal ENABLE to the Tclz/Tchz path 22. The Tco gate 32 has an input that receives the signal CLK, an input that receives the signal CNTL2 and an output that presents the signal CLK to the Tco propagation path 24. When the circuit 10 is operated in the pipeline mode, the path 24 presents the signal CLK to a clock input of the Tco register 42. The Tco register 42 presents the signal IO to the buffer 40.
The LOW to HIGH (i.e., enable) and HIGH to LOW (i.e., disable) edges of the signal ENABLE corresponding to the Tclz and Tchz parameters, respectively, need to propagate through the circuit 10 with equal speed and priority. However, the Tco parameter path 24 only has to propagate the rising (LOW to HIGH) edge of the output register clock signal CLK to the output buffer 26 from the central control logic 20. The Tco parameter rising edge logic is skewed to favor the clock signal CLK rising edge. However, the Tclz/Tchz parameter path 22 cannot favor either the rising or the trailing edge of the signal ENABLE. As a result, the Tco parameter path 24 is faster than the Tclz/Tchz parameter path 22. Propagation of the HIGH to LOW and LOW to HIGH edges of the signal ENABLE at different speeds can cause delay imbalance in the buffer 40 between the Tco parameter and the Tclz/Tchz parameters.
Referring to FIG. 2, a block diagram illustrating another conventional buffer control circuit 10xe2x80x2 is shown. The circuit 10xe2x80x2 represents a previous attempt to resolve the delay imbalance in the buffer 40. The circuit 10xe2x80x2 is implemented similarly to the circuit 10. The circuit 10xe2x80x2 includes the paths 22 and 24, a controller 20xe2x80x2 (i.e., the Tco gate 32a and a clock gate 32b), and an output buffer circuit 26xe2x80x2. Each of the circuits 26xe2x80x2 in the RAM includes the tristate register circuit 30 as well as the buffer 40 and the Tco register 42. However, the register 30 requires time to setup (i.e., Tsetup) and to hold (i.e., Thold). The times Tsetup and Thold delay and/or skew the timing of the signal CLK. As a result, the circuit 10xe2x80x2 fails to provide an adequate solution to the delay imbalance in the buffer 40.
It would be desirable to have an output buffer control circuit that (i) matches the timing of the enable/disable signals to a preferred path timing, (ii) presents the buffer control signal at high and low logic states with substantially equal timing, (iii) reduces or eliminates buffer delay imbalance, and/or (iv) reduces or eliminates setup and hold timing issues.
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate one or more first control signals in response to (i) a clock signal and (ii) one or more second control signals. The second circuit may be (i) coupled to the first circuit via one or more path circuits and (ii) configured to present an output signal in response to the one or more first control signals. All of the one or more first control signals may have a preferred edge skew.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a dual tristate path output buffer control that may (i) match the timing of the enable/disable signals to a preferred path, (ii) provide substantially equal timing when the buffer control signal is at high and low logic states, (iii) reduce or eliminate buffer delay imbalance, (iv) reduce or eliminate setup and hold timing issues, and/or (v) provide substantially equal output buffer assertion/de-assertion timing.